Senior Chip Lead-Physical Design
Location : Bangalore
10 - 20 years of physical design experience
Strong in Physical design, STA, Synthesis and Low Power Design
Nice to have experience in Processors / Finfet
Responsibilities will include block level ownership of design, unit level verification, design reviews.
Work with multiple sites in a team environment particularly with offices in the US.
BS / MS in EE/CSE from a reputed University.
Good knowledge of EDA tools from Synopsys, Cadence and Mentor required. In particular experience with PTSI, First Encounter, Nanoroute, Calibre, StarRC, and Conformal is essential.
Good knowledge of VLSI process and device characteristics, to make optimal trade-off between performance and power.
Good knowledge of standard cell libraries - circuit design and cell layout.
Good understanding of static timing analysis (STA), EM/IR and sign-off flows.
Strong hands-on experience with:
Low power design techniques.
Floor planning, place & route, power and clock distribution, pin placement and timing constraints generation.
Timing convergence using high speed design techniques with signal integrity & EM/IR.
Physical design verification.
Functional verification at various levels of design hierarchy with respect to golden RTL by formal methods.
Prior experience with 40nm or finer geometries.
Good software and scripting skills (perl, python, tcl).
Self-driven individual and an excellent team player experienced in working with remote teams.
Must have good communication skills and the ability and desire to work as a team.
Candidate is expected to work on RTL to GDS for processor core designs, optimizing the implementations for power, timing and area.
To be responsible for and own all aspects of physical design and physical verification effort at a block level. Will also need to help out at the top level.
Develop, support and maintain physical design flows and methodologies.
Work closely with the design team to accomplish the objectives.
Expert in physical design of high frequency chips with emphasis on successful timing closure.
Excellent understanding of geometry/ process/ device technology implications on physical design.
Expert in physical design verification.
Independent, self-driven, strong team player.
"Mining the knowledge Community"
The Human Capital
"Mining The Knowledge Community"
Email : email@example.com
|Salary:|| Not Disclosed by Recruiter |
|Industry:|| Semiconductors / Electronics |
|Functional area:|| IT Software - Embedded , EDA , VL|
|Role:||Team Lead/Technical Lead|
|Role category:||Programming & Design|
|Key skills:|| Physical Design PTSI First Encounter Nanoroute Calibre StarRc Conformal STA EM IR EMIR Floor Planning RTL to GDS RTL to GDSII RTL to GDS2 Synthesis Finfet PrimeTime Design Compile|
|Any graudate:||B.Tech/B.E. - Any Specialization, Computers, Electrical|
|Post graduate:||M.Tech - Any Specialization, Computers, Electrical, M.Sc - Any Specialization, Computers|
|Doctrate:||Any Doctorate - Any Specialization, Any Specialization, Doctorate Not Required|
| Please refer to the Job description above |
The Human Capital
AppliedMicro is an innovative global leader in system-on-a-chip semiconductors for high-speed communications and high-performance embedded processing. Leveraging 30 years of expertise, AppliedMicro products deliver an ideal combination of high-performance, low-power and low cost across optical transport, datacenter connectivity, enterprise, small-to-medium business and consumer markets. Combining both hardware and software, AppliedMicro offers advanced packet processing capabilities that enable rapid time to market, high-reliability, increased capacity and energy efficiency for the world's leading equipment developers.
AppliedMicro is headquartered in Sunnyvale, Calif., with offices and research facilities in North America, Asia and Europe. The India offices are located in Bangalore and Pune. For more information about AppliedMicro, visit the company"s website at www.apm.com.